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CD4027BE CD4027 CMOS Dual J-K Master-Slave Flip-Flop IC Breadboard-Friendly DIP-16 (Pack of 10)

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$12.49

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  • Set-Reset capability, Standardized, symmetrical output characteristics
  • Static flip-flop operation — retains state indefinitely with clock level either "high" or "low"
  • Medium speed operation — 16 MHz (typ.) clock toggle rate at 10 V, Noise margin (full package-temperature range) = 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
  • 5-V, 10-V, and 15-V parametric ratings, 100% tested for quiescent current at 20 V, Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
  • Applications: Registers, Counters, Control Circuits


The CD4027B s a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input signals. Buffered Q and Q\ signals are provided as outputs. This input-output arrangement provides for compatible operation with the RCA-CD4013B dual D-type flip-flop.
The CD4027B is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs along with internal self-steering control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.